Intel “Razor Lake-AX” to Pack 700 TOPS of AI Compute

What Intel Just Announced: 700 TOPS, On-Die

At the Semiconductors Powering Humanoids summit in South Korea, Intel senior vice president Cho Min-sung outlined an ambitious next-generation platform: Intel “Razor Lake-AX.”

The headline number is hard to miss: 700 TOPS of AI compute on die (at INT8/FP8 precision). If this figure holds through productization, it positions Razor Lake-AX as one of the most AI-forward client SoCs Intel has publicly discussed—less like a traditional laptop chip and more like a compact heterogeneous compute module.

In Intel’s comparison, Razor Lake-AX’s 700 TOPS would be 3.88× higher than the current “Panther Lake” mobile chips cited at 180 TOPS total compute.

Why TOPS Matters (and Why It Can Be Confusing)

If you’re new to AI hardware specs, TOPS stands for Tera Operations Per Second—a broad measure of how many math operations a chip can do in a second.

A few important clarifications:

• TOPS isn’t a single “AI speed” number. It depends on precision (INT8 vs FP8 vs FP16, etc.), sparsity, and the workload.
• Vendors often quote peak throughput under ideal conditions.
• Real-world performance also depends on memory bandwidth, software, and how well workloads map to the chip’s accelerators.

That said, TOPS is still useful for understanding directionally how much AI acceleration a platform is targeting. A jump from 180 TOPS to 700 TOPS signals Intel is planning a major increase in on-device AI capability, especially for tasks like local inference, multimodal assistants, and AI-enhanced creative workflows.

For teams building products around on-device models, it’s also a reminder that software strategy matters as much as silicon. If you’re mapping out roadmaps for local inference, model optimization, and deployment pipelines, this pairs naturally with work like Generative AI Development for Intelligent Solutions—because raw compute only becomes “intelligence” when the toolchain and product design are ready.

Where the 700 TOPS Likely Comes From: A Big iGPU + CPU Complex

According to the report, the uplift is expected to come “primarily derived from a large integrated GPU alongside a substantial CPU complex.”

This mirrors the broader industry trend: for client platforms, the GPU increasingly does double duty—graphics plus a major share of AI throughput.

Intel’s rumored iGPU configurations for Razor Lake-AX include:

• A 16-core iGPU variant
• A flagship 32-core iGPU variant

Both are expected to be based on Intel’s Xe3 graphics IP, which is already associated with Panther Lake.

Xe3 and the Arc Connection

The report suggests Razor Lake-AX could be nearly three times as powerful as the current Arc B390 referenced in Intel’s PTL (Panther Lake) lineup context.

While “3×” claims should always be treated cautiously without standardized benchmarks, the implication is clear: Intel is aiming for an iGPU that’s not just “good enough,” but large and central to the SoC’s identity—especially for AI.

You can learn more about Intel’s broader ecosystem at Intel.

Tech Specs (What’s Known vs. What’s Rumored)

This section consolidates the concrete details and the credible rumors mentioned in the source context.

Confirmed / Stated Publicly

• Product/platform name: Intel Razor Lake-AX
• AI compute claim: 700 TOPS on die
• Precision referenced: INT8/FP8
• Relative claim: 3.88× Panther Lake (cited at 180 TOPS)
• Timeframe: Expected after Nova Lake, with an ETA around 2028

Reported / Rumored (Not Officially Final)

• iGPU options: 16-core and 32-core iGPU variants
• Graphics IP: Intel Xe3 (some community discussion suggests it could be Xe3P)
• GPU die size: ~162.84 mm² (reported)
• Packaging/interconnect: likely EMIB + Foveros 3D
• Memory: return of on-package LPDDR5X/LPDDR6
• Socket/package: BGA-4326 (4,326 pins), similar in pin-count class to some Xeon packages

For readers unfamiliar with Intel’s advanced packaging terms:

• EMIB (Embedded Multi-die Interconnect Bridge) is Intel’s approach to high-bandwidth die-to-die connections without a full silicon interposer.
• Foveros 3D is Intel’s 3D stacking technology, enabling vertical integration of compute tiles.

These technologies matter because a platform combining a large GPU tile, CPU tiles, and on-package memory needs very high bandwidth and low latency between components.

On-Package Memory Is (Reportedly) Coming Back

One of the more interesting details: Intel is reportedly planning to reintroduce on-package memory for Razor Lake-AX.

That’s notable because Intel previously indicated that Core Ultra 200V “Lunar Lake” would be the last design with on-package memory. Now, the rumor says Razor Lake-AX could bring back:

• On-package LPDDR5X
• Potentially on-package LPDDR6

Why On-Package Memory Matters

On-package memory can offer:

• Higher effective bandwidth (shorter traces, tighter signaling)
• Lower power for memory access in some scenarios
• Smaller system designs (fewer external memory routing constraints)

But it also comes with trade-offs:

• Less upgradeability (memory is effectively fixed)
• Potential cost increases and packaging complexity
• More constraints on SKU planning and supply chain

If Intel is pairing a very large iGPU with strong AI ambitions, on-package memory makes strategic sense: AI and graphics workloads are often bandwidth-hungry, and the platform may be designed to keep data close to compute.

For context on memory standards and LPDDR roadmaps, see JEDEC.

A Massive Package: BGA-4326 and “Client Chip, Server Attitude”

The report also mentions Razor Lake-AX could use a BGA-4326 package—4,326 pins—which is described as similar to what Intel’s Xeon CPUs typically use.

That doesn’t automatically mean it’s a server chip. But it does imply:

• A large, complex module with lots of I/O and power delivery needs
• Potentially more lanes, more memory interfaces, or more die-to-die connections
• A design that may target high-end mobile workstations, compact desktops, or specialized OEM systems rather than thin-and-light mainstream laptops

In other words, “AX” may represent a class of machines where AI throughput is a first-class spec, not a footnote.

Manufacturing: Still Unclear, but Packaging Will Be Key

The source notes it’s unclear where Intel will manufacture this chip.

What is emphasized is that the design likely relies heavily on chiplet-style integration and advanced packaging (EMIB + Foveros 3D). That approach can allow Intel to:

• Mix different process nodes or foundry sources
• Scale iGPU size independently from CPU tiles
• Optimize yields and costs by splitting large designs into multiple dies

If Razor Lake-AX really is anchored by a large GPU tile and on-package memory, packaging becomes as important as the silicon itself.

What Happened to Nova Lake-AX?

The report adds an important roadmap detail: Intel had previously considered a “Nova Lake-AX” SoC with:

• 48 Xe3 cores
• A 28-core CPU cluster

That plan is reportedly on hold, and the “AX” generation will not debut with Nova Lake. Instead, Intel plans to launch “AX” chips after Nova Lake, with Razor Lake-AX expected around 2028.

For buyers, this matters because it suggests:

• The “AX” concept is real, but timelines and naming can shift
• Intel is likely iterating on what “AX” should be (performance tier, form factors, pricing)

What 700 TOPS Could Enable on PCs (Beginner-Friendly Examples)

Assuming Intel’s 700 TOPS number translates into strong real-world AI performance, here are practical categories where users could benefit—without needing a data center:

• On-device assistants that can run larger models locally for privacy and responsiveness
• Real-time translation and transcription with less cloud dependency
• AI image and video workflows (denoise, upscaling, background replacement, object removal)
• Developer tooling (local code completion, embeddings, search, smaller agents)
• Robotics/humanoids edge compute—fitting given the summit theme—where latency and offline operation matter

Of course, software support will decide how much of this is “day one” reality. The ecosystem—drivers, runtimes, frameworks, and ISV adoption—will determine whether users feel the difference.

Competitive Context: The Race to Put AI on the Die

Intel’s claim lands in a market where everyone is pushing “AI PCs,” but with different approaches:

• Some platforms emphasize NPU TOPS (dedicated neural engines)
• Others lean on GPU compute for broader AI acceleration
• Many real-world apps use a mix of CPU + GPU + NPU

Razor Lake-AX, as described, sounds like a “more GPU-forward” AI story—especially if the 32-core Xe3 iGPU is central to hitting 700 TOPS.

This is also where product strategy intersects with business strategy: companies adopting AI at the edge will be balancing cost, privacy, manageability, and performance. For a broader perspective on aligning AI capabilities with organizational outcomes, see Building Intelligent Systems for the Future of Business.

What to Watch Next (Between Now and 2028)

Because Razor Lake-AX is still far out, the most useful approach is to watch for “breadcrumbs” that validate (or revise) today’s claims.

Key signals to look for:

• More concrete SKU details: CPU core counts, GPU core definitions, clocks, power targets
• Memory configuration clarity: how much on-package memory, speeds, and whether LPDDR6 is truly planned
• Software stack commitments: developer tooling, AI runtimes, and performance demos
• Platform positioning: mainstream mobile vs workstation vs compact desktop vs edge modules
• Packaging disclosures: confirmation of EMIB/Foveros usage and tile breakdowns

Bottom Line

Intel’s Razor Lake-AX tease is less about incremental gains and more about a bold bet: 700 TOPS on-die AI compute backed by a very large Xe3-based iGPU, potentially paired with on-package LPDDR5X/LPDDR6 and advanced packaging like EMIB and Foveros 3D.

If the platform arrives on schedule (the report points to 2028) and Intel can translate peak TOPS into real application performance, Razor Lake-AX could mark a shift toward GPU-heavy, bandwidth-rich client SoCs that treat AI as a primary workload—rather than an add-on.

Source context: TechPowerUp report citing statements at the Semiconductors Powering Humanoids summit and additional reporting attributed to The Elec.

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